1. Field of the Invention
The present invention relates generally to semiconductor memory devices, and, more particularly, to sensing circuitry yielding an improved read access time.
2. Description of the Related Art
In many computer systems, high speed redundant memories are commonly used to store recently used data or data that will likely be needed very soon. These memories are referred to as cache memories. A cache memory mirrors data stored in the main memory of the computer system, but because of its significantly higher speed, the cache memory may supply data more quickly. Typically, dynamic random access memories (DRAMs) (synchronous or asynchronous) are used as main memory devices due to their relatively high densities. Cache memories are typically static random access memories (SRAMs). SRAMs generally have lower densities than DRAMs, but they are significantly faster. Because of their higher speeds of operation, SRAMs find additional application in various computer systems, and their use as cache memories is simply one example of their application. Other types of memories that are commonly found in computer systems include Flash, EAPROMs, EEPROMs, EPROMs, PROMs, ROMs, and variations of any of the above.
Various configurations of memory cells have been designed and developed to reduce the silicon area consumed by the cells, to increase the operating speed of the devices, and to achieve numerous other goals. Traditionally, for example, SRAM cells have been designed with either four transistors and two polysilicon load resistors, or six transistors, using two PMOS devices as active load devices. Reduction of silicon area consumed by an SRAM cell, i.e., increasing the density of cells in an SRAM device, can be realized by using cells with as few transistors as possible. In many stand-alone SRAM applications, polysilicon load resistors have replaced the PMOS load transistors in the six-transistor cells. Resistive load inverters, however, have very asymmetrical switching transients and have steady-state standby DC power dissipation. Accordingly, many SRAMs embedded in microprocessors have continued to use the six-transistor cells. Other SRAM designs have also been proposed. For example, U.S. Pat. No. 6,011,726, issued Jan. 4, 2000, entitled xe2x80x9cFour Device SRAM Cell With Single Bit Line,xe2x80x9d describes a cell having four transistors and one polysilicon load resistor. Other approaches have used only four transistors and have relied upon the sub-threshold leakage of the transfer devices in place of load resistors or transistors. These types of cells have been referred to as xe2x80x9cloadlessxe2x80x9d four-transistor CMOS SRAM cells with no polysilicon resistor.
Besides reducing silicon area consumed by a cell, other approaches have been explored in an effort to increase the efficiency of memories. Moreover, various approaches have been proposed to increase the speed with which memory cells may be accessed, for example, as when reading the contents of the cell. Single-ended sense amplifiers as well as a varied assortment of dual input sense amplifiers have been proposed and used. Regardless of the type of memory or the configuration of the memory cell, increasing the speed with which the cell may be accessed (i.e., decreasing access time) is, and will remain, a major concern.
By way of background and example only, FIG. 1 illustrates a conventional CMOS SRAM cell 10 in combination with a cross-coupled sense amplifier 20. The cell 10 could as well be a DRAM cell or some other memory cell type. The cell 10 is coupled to the sense amplifier 20 by way of a bit line 58 and a complementary bit line 60. The cell 10 includes two NMOS transistors 32, 34 and two resistors 36, 38. The transistor 32 and the resistor 36 are coupled in series between a power supply voltage 42 and a ground potential 44. The transistor 34 and the resistor 38 are also coupled in series between the power supply voltage 42 and the ground potential 44. The gate terminal of the transistor 32 is coupled to a node 48 between the transistor 34 and the resistor 38, and the gate terminal of the transistor 34 is coupled to a node 46 between the transistor 32 and the resistor 36. An access transistor 52 couples the node 46 of the cell 10 to the complementary bit line 60, and an access transistor 54 couples the node 48 of the cell 10 to the bit line 58. An access signal will be provided on line 56 when the cell 10 is to be coupled to the bit line 58 and the complementary bit line 60 so that a datum stored in the cell 10 may be read by way of the sense amplifier 20. The cell 10 is a symmetrical SRAM cell.
The sense amplifier 20 includes two NMOS transistors 62, 64 and two PMOS transistors 66, 68. The transistor 62 and the transistor 66 are coupled in series between a power supply voltage 42 and a ground potential 44, and the transistor 64 and the transistor 68 arc coupled in series between the power supply voltage 42 and the ground potential 44. The gate of the transistor 62 is coupled to a node 72 between the transistors 64 and 68, while the gate of the transistor 64 is coupled to a node 70 between the transistors 62 and 66. The node 72 of the sense amplifier 20 is coupled to the bit line 58, while the node 70 of the sense amplifier 20 is coupled to the complementary bit line 60. When the datum in the cell 10 is to be read, the bit line 58 and the complementary bit line 60 are each pre-charged to a value of approximately one-half the full power supply voltage, or VDD/2. A datum is represented by one of two possible states in which the cell 10 may be maintained. For example, a logical xe2x80x9czeroxe2x80x9d may be represented in the cell 10 when the node 46 is at or near the ground potential and the node 48 is at or near the power supply potential. A logical xe2x80x9conexe2x80x9d might be indicated by the node 48 being at or close to the ground potential and the node 46 being at or close to the power supply potential.
For purposes of explanation, assume the cell 10 stores a logical xe2x80x9cone,xe2x80x9d meaning the node 48 is at or near the ground potential and the node 46 is at or near the power supply potential. Because the cell 10 is symmetrical, sensing a logical xe2x80x9conexe2x80x9d or logical xe2x80x9czeroxe2x80x9d will require the same amount of time. After the bit line 58 and the complementary bit line 60 have been pre-charged to approximately one-half the power supply potential (by circuitry not shown), an access signal is provided on the line 56 to turn on the access transistors 52 and 54 to couple the nodes 46 and 48 to the complementary bit line 60 and the bit line 58, respectively. Because the node 48 is at a low potential, the transistor 32 is in an xe2x80x9coff,xe2x80x9d or non-conducting, state, and because the node 46 is at a high potential, the transistor 34 is in its xe2x80x9con,xe2x80x9d or conducting, state. When the nodes 46 and 48 are coupled to the complementary bit line 60 and the bit line 58, respectively, the conducting transistor 34 will begin to pull the potential on tile bit line 58 toward the ground potential. Conversely, because the transistor 32 remains in a non-conducting, or essentially non-conducting, state, the potential on the complementary bit line 60 is pulled up toward the power supply potential through the resistor 36. As a differential voltage appears between the bit line 58 and the complementary bit line 60, the sense amplifier 20 will amplify the difference and drive the bit line 58 to ground potential and the complementary bit line 60 to the power supply potential. Output circuitry (not shown) will utilize the potential on the bit line 58 or the potential on the complementary bit line 60, or both, to produce an output signal indicative of the datum stored in the cell 10.
As further background and example, FIG. 2 illustrates a read operation on a conventional SRAM cell 100 using single-sided sensing when the bit lines are pre-charged to a high potential (rather than VDD/2). The cell 100 in FIG. 2 is identical to the cell 10 in FIG. 1. But, the cell 10 in FIG. 1 is coupled to a two-input sensing amplifier, whereas the sensing amplifier in FIG. 2 is single-sided. Depending on the state of the memory cell 100, either transistor 102 or transistor 104 will be conducting while the other is not conducting. When a transfer device (e.g., transistor 118) is activated to read the cell 100, the bit line is initially at a high potential, and if the transistor 104 in the cell is in a conducting state, it pulls the bit line toward ground potential. In the example of FIG. 2, the signal on the line 126 to the sense amplifier is in reality only single-sided, or single-ended. The signal is not differential and, as such, is more susceptible to common mode noise.
Static CMOS and static pseudo-NMOS logic circuits are widely used in CMOS technology in integrated circuits. Static CMOS has, for example, been widely used in the design of microprocessors. One problem related to static circuits is the asymmetrical switching characteristics, that is, the time required to pull down the output is generally much shorter than the time required to pull up the input. Thus, the normal stage propagation delay, tp, is then determined primarily by the slow pull up time. If a series of static CMOS logic circuits, in the simplest case inverters, are connected in a chain, then when the circuit is enabled or activated and the input changes state, every output must change state. This results in a long signal delay through the chain, is wasteful of energy, and causes high power dissipation.
The present invention is directed to sensing circuitry that provides decreased read access times while achieving greater stability and reliability in operation. The present invention relates to sensing circuitry where the output is predicted in advance of reading a memory cell. This prediction is reflected in pre-charging at output nodes in the circuitry. While, on average, this prediction may be wrong approximately one-half the time, the result in one exemplary embodiment is an overall reduction in access time of about 50%.
In one aspect of the present invention, a sense amplifier for an integrated circuit memory comprises first and second output nodes, and a pre-charged transistor coupled to the second output node and adapted to pre-charge the second output node to approximately a first power supply potential. The first output node is adapted to be pre-charged to a second power supply potential, and the sense amplifier is adapted to provide first and second output signals at the first and second output nodes, respectively, in response to at least a first input signal.
In another aspect of the present invention, a memory cell and sense amplifier combination in an integrated circuit comprises first and second output nodes, a first transistor coupled between a first power supply node and the first output node, a second transistor coupled between the first output node and a second power supply node, the second transistor having a gate terminal coupled to a first bit line, and a third transistor coupled between the first power supply node and the second output node. The combination further comprises a fourth transistor coupled between the first power supply node and the second output node, the fourth transistor having a gate terminal coupled to a clock signal line, the fourth transistor being adapted to pre-charge the second output node to approximately a potential at the first power supply node. A fifth transistor is coupled between the second output node and the second power supply node, and the fifth transistor has a gate terminal coupled to a second bit line. The first output node is adapted to be pre-charged to approximately a potential at the second power supply node, and the sense amplifier is adapted to provide first and second output signals at the first and second output nodes, respectively, in response to signals on the first and second bit lines and a clock signal on the clock signal line. A memory cell is adapted to be controllably coupled to the first bit line.
In yet another aspect of the present invention, a sensing circuit comprises a sense amplifier adapted to receive an input signal from a memory cell and to provide a first output signal on a first output node. An output amplifier is adapted to receive the first output signal and to provide a second output signal on a second output node. The sense amplifier comprises a sense amplifier pre-charge transistor coupled between a first power supply node and the first output node, and the sense amplifier pre-charge transistor is adapted to pre-charge the first output node to approximately a first power supply potential. The output amplifier comprises an output amplifier pre-charge transistor coupled between the first power supply node and the second output node, and the output amplifier pre-charge transistor is adapted to pre-charge the second output node to approximately the first power supply potential.
In yet another aspect of the present invention, a sensing circuit comprises a sense amplifier adapted to receive an input signal from a memory cell and a reference signal. The sense amplifier is adapted to produce a first output signal indicative of a difference between the input signal and the reference signal. An amplifier circuit is coupled to the sense amplifier and is adapted to receive the first output signal from the sense amplifier. The amplifier circuit is adapted to produce an amplifier output signal on an output line. The amplifier circuit comprises a pre-charge transistor coupled between a first power supply node and the output node, and the pre-charge transistor is adapted to pre-charge the output node to approximately a first power supply potential.